The present invention relates to semiconductor processing; and more particularly to a method of etching a dielectric with minimal organic mask.
Pillar arrays are an increasingly desired geometric configuration for upcoming technologies such as, for example, spin-transfer torque magnetoresistive random access memory (STT-MRAM). However, there are many challenges involved in directly patterning pillars, such as collapse at high aspect ratios and control of critical dimensions (CD) and sidewall angles. The use of image reversal process flows to form pillars from hole (via) arrays can improve fidelity due to the higher structural integrity of hole arrays, however, the hole array is often formed in a carbon-based material in order to facilitate removal by ashing chemistries, e.g., in downstream plasmas or through wet chemistries. As these chemistries have a significant isotropic etch component, this has negative implications for transferring patterns at very tight pitches.
There is thus a need to provide a process that will directly pattern pillars using entirely plasma etch processes designed to be largely anisotropic, which offer better control of CD and sidewall angles than wet etch patterning or predominantly isotropic plasma etch conditions.